[−][src]Enum lpc55s6x_pac::adc0::cfg::PWRENW
Values that can be written to the field PWREN
Variants
PWREN_0
ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
PWREN_1
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed.
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