[−][src]Enum lpc55s6x_pac::adc0::cfg::PWRENR
Possible values of the field PWREN
Variants
PWREN_0
ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
PWREN_1
ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed.
Methods
impl PWRENR
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pub fn bit_is_clear(&self) -> bool
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Returns true
if the bit is clear (0)
pub fn bit_is_set(&self) -> bool
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Returns true
if the bit is set (1)
pub fn bit(&self) -> bool
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Value of the field as raw bits
pub fn is_pwren_0(&self) -> bool
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Checks if the value of the field is PWREN_0
pub fn is_pwren_1(&self) -> bool
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Checks if the value of the field is PWREN_1
Trait Implementations
impl PartialEq<PWRENR> for PWRENR
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impl Copy for PWRENR
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impl Debug for PWRENR
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impl Clone for PWRENR
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Auto Trait Implementations
Blanket Implementations
impl<T> From<T> for T
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impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Same<T> for T
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type Output = T
Should always be Self