[][src]Struct lpc55s6x_pac::usbphy::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { pub pwd: PWD, pub pwd_set: PWD_SET, pub pwd_clr: PWD_CLR, pub pwd_tog: PWD_TOG, pub tx: TX, pub tx_set: TX_SET, pub tx_clr: TX_CLR, pub tx_tog: TX_TOG, pub rx: RX, pub rx_set: RX_SET, pub rx_clr: RX_CLR, pub rx_tog: RX_TOG, pub ctrl: CTRL, pub ctrl_set: CTRL_SET, pub ctrl_clr: CTRL_CLR, pub ctrl_tog: CTRL_TOG, pub status: STATUS, pub debug0: DEBUG0, pub debug0_set: DEBUG0_SET, pub debug0_clr: DEBUG0_CLR, pub debug0_tog: DEBUG0_TOG, pub debug1: DEBUG1, pub debug1_set: DEBUG1_SET, pub debug1_clr: DEBUG1_CLR, pub debug1_tog: DEBUG1_TOG, pub version: VERSION, pub pll_sic: PLL_SIC, pub pll_sic_set: PLL_SIC_SET, pub pll_sic_clr: PLL_SIC_CLR, pub pll_sic_tog: PLL_SIC_TOG, pub usb1_vbus_detect: USB1_VBUS_DETECT, pub usb1_vbus_detect_set: USB1_VBUS_DETECT_SET, pub usb1_vbus_detect_clr: USB1_VBUS_DETECT_CLR, pub usb1_vbus_detect_tog: USB1_VBUS_DETECT_TOG, pub usb1_vbus_det_stat: USB1_VBUS_DET_STAT, pub usb1_chrg_detect: USB1_CHRG_DETECT, pub usb1_chrg_detect_set: USB1_CHRG_DETECT_SET, pub usb1_chrg_detect_clr: USB1_CHRG_DETECT_CLR, pub usb1_chrg_detect_tog: USB1_CHRG_DETECT_TOG, pub usb1_chrg_det_stat: USB1_CHRG_DET_STAT, pub anactrl: ANACTRL, pub anactrl_set: ANACTRL_SET, pub anactrl_clr: ANACTRL_CLR, pub anactrl_tog: ANACTRL_TOG, // some fields omitted }

Register block

Fields

pwd: PWD

0x00 - USB PHY Power-Down Register

pwd_set: PWD_SET

0x04 - USB PHY Power-Down Register

pwd_clr: PWD_CLR

0x08 - USB PHY Power-Down Register

pwd_tog: PWD_TOG

0x0c - USB PHY Power-Down Register

tx: TX

0x10 - USB PHY Transmitter Control Register

tx_set: TX_SET

0x14 - USB PHY Transmitter Control Register

tx_clr: TX_CLR

0x18 - USB PHY Transmitter Control Register

tx_tog: TX_TOG

0x1c - USB PHY Transmitter Control Register

rx: RX

0x20 - USB PHY Receiver Control Register

rx_set: RX_SET

0x24 - USB PHY Receiver Control Register

rx_clr: RX_CLR

0x28 - USB PHY Receiver Control Register

rx_tog: RX_TOG

0x2c - USB PHY Receiver Control Register

ctrl: CTRL

0x30 - USB PHY General Control Register

ctrl_set: CTRL_SET

0x34 - USB PHY General Control Register

ctrl_clr: CTRL_CLR

0x38 - USB PHY General Control Register

ctrl_tog: CTRL_TOG

0x3c - USB PHY General Control Register

status: STATUS

0x40 - USB PHY Status Register

debug0: DEBUG0

0x50 - USB PHY Debug Register 0

debug0_set: DEBUG0_SET

0x54 - USB PHY Debug Register 0

debug0_clr: DEBUG0_CLR

0x58 - USB PHY Debug Register 0

debug0_tog: DEBUG0_TOG

0x5c - USB PHY Debug Register 0

debug1: DEBUG1

0x70 - UTMI Debug Status Register 1

debug1_set: DEBUG1_SET

0x74 - UTMI Debug Status Register 1

debug1_clr: DEBUG1_CLR

0x78 - UTMI Debug Status Register 1

debug1_tog: DEBUG1_TOG

0x7c - UTMI Debug Status Register 1

version: VERSION

0x80 - UTMI RTL Version

pll_sic: PLL_SIC

0xa0 - USB PHY PLL Control/Status Register

pll_sic_set: PLL_SIC_SET

0xa4 - USB PHY PLL Control/Status Register

pll_sic_clr: PLL_SIC_CLR

0xa8 - USB PHY PLL Control/Status Register

pll_sic_tog: PLL_SIC_TOG

0xac - USB PHY PLL Control/Status Register

usb1_vbus_detect: USB1_VBUS_DETECT

0xc0 - USB PHY VBUS Detect Control Register

usb1_vbus_detect_set: USB1_VBUS_DETECT_SET

0xc4 - USB PHY VBUS Detect Control Register

usb1_vbus_detect_clr: USB1_VBUS_DETECT_CLR

0xc8 - USB PHY VBUS Detect Control Register

usb1_vbus_detect_tog: USB1_VBUS_DETECT_TOG

0xcc - USB PHY VBUS Detect Control Register

usb1_vbus_det_stat: USB1_VBUS_DET_STAT

0xd0 - USB PHY VBUS Detector Status Register

usb1_chrg_detect: USB1_CHRG_DETECT

0xe0 - USB PHY Charger Detect Control Register

usb1_chrg_detect_set: USB1_CHRG_DETECT_SET

0xe4 - USB PHY Charger Detect Control Register

usb1_chrg_detect_clr: USB1_CHRG_DETECT_CLR

0xe8 - USB PHY Charger Detect Control Register

usb1_chrg_detect_tog: USB1_CHRG_DETECT_TOG

0xec - USB PHY Charger Detect Control Register

usb1_chrg_det_stat: USB1_CHRG_DET_STAT

0xf0 - USB PHY Charger Detect Status Register

anactrl: ANACTRL

0x100 - USB PHY Analog Control Register

anactrl_set: ANACTRL_SET

0x104 - USB PHY Analog Control Register

anactrl_clr: ANACTRL_CLR

0x108 - USB PHY Analog Control Register

anactrl_tog: ANACTRL_TOG

0x10c - USB PHY Analog Control Register

Auto Trait Implementations

impl Send for RegisterBlock

impl !Sync for RegisterBlock

Blanket Implementations

impl<T> From<T> for T[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Same<T> for T[src]

type Output = T

Should always be Self