Struct lpc55s6x_pac::usbfsh::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub hcrevision: HCREVISION,
    pub hccontrol: HCCONTROL,
    pub hccommandstatus: HCCOMMANDSTATUS,
    pub hcinterruptstatus: HCINTERRUPTSTATUS,
    pub hcinterruptenable: HCINTERRUPTENABLE,
    pub hcinterruptdisable: HCINTERRUPTDISABLE,
    pub hchcca: HCHCCA,
    pub hcperiodcurrented: HCPERIODCURRENTED,
    pub hccontrolheaded: HCCONTROLHEADED,
    pub hccontrolcurrented: HCCONTROLCURRENTED,
    pub hcbulkheaded: HCBULKHEADED,
    pub hcbulkcurrented: HCBULKCURRENTED,
    pub hcdonehead: HCDONEHEAD,
    pub hcfminterval: HCFMINTERVAL,
    pub hcfmremaining: HCFMREMAINING,
    pub hcfmnumber: HCFMNUMBER,
    pub hcperiodicstart: HCPERIODICSTART,
    pub hclsthreshold: HCLSTHRESHOLD,
    pub hcrhdescriptora: HCRHDESCRIPTORA,
    pub hcrhdescriptorb: HCRHDESCRIPTORB,
    pub hcrhstatus: HCRHSTATUS,
    pub hcrhportstatus: HCRHPORTSTATUS,
    pub portmode: PORTMODE,
    // some fields omitted
}

Register block

Fields

hcrevision: HCREVISION

0x00 - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC)

hccontrol: HCCONTROL

0x04 - Defines the operating modes of the HC

hccommandstatus: HCCOMMANDSTATUS

0x08 - This register is used to receive the commands from the Host Controller Driver (HCD)

hcinterruptstatus: HCINTERRUPTSTATUS

0x0c - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits

hcinterruptenable: HCINTERRUPTENABLE

0x10 - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt

hcinterruptdisable: HCINTERRUPTDISABLE

0x14 - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt

hchcca: HCHCCA

0x18 - Contains the physical address of the host controller communication area

hcperiodcurrented: HCPERIODCURRENTED

0x1c - Contains the physical address of the current isochronous or interrupt endpoint descriptor

hccontrolheaded: HCCONTROLHEADED

0x20 - Contains the physical address of the first endpoint descriptor of the control list

hccontrolcurrented: HCCONTROLCURRENTED

0x24 - Contains the physical address of the current endpoint descriptor of the control list

hcbulkheaded: HCBULKHEADED

0x28 - Contains the physical address of the first endpoint descriptor of the bulk list

hcbulkcurrented: HCBULKCURRENTED

0x2c - Contains the physical address of the current endpoint descriptor of the bulk list

hcdonehead: HCDONEHEAD

0x30 - Contains the physical address of the last transfer descriptor added to the 'Done' queue

hcfminterval: HCFMINTERVAL

0x34 - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun

hcfmremaining: HCFMREMAINING

0x38 - A 14-bit counter showing the bit time remaining in the current frame

hcfmnumber: HCFMNUMBER

0x3c - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD

hcperiodicstart: HCPERIODICSTART

0x40 - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list

hclsthreshold: HCLSTHRESHOLD

0x44 - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF

hcrhdescriptora: HCRHDESCRIPTORA

0x48 - First of the two registers which describes the characteristics of the root hub

hcrhdescriptorb: HCRHDESCRIPTORB

0x4c - Second of the two registers which describes the characteristics of the Root Hub

hcrhstatus: HCRHSTATUS

0x50 - This register is divided into two parts

hcrhportstatus: HCRHPORTSTATUS

0x54 - Controls and reports the port events on a per-port basis

portmode: PORTMODE

0x5c - Controls the port if it is attached to the host block or the device block