[−][src]Struct lpc55s6x_pac::syscon::RegisterBlock
Register block
Fields
memoryremap: MEMORYREMAP0x00 - Memory Remap control register
ahbmatprio: AHBMATPRIO0x10 - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest
cpu0stckcal: CPU0STCKCAL0x38 - System tick calibration for secure part of CPU0
cpu0nstckcal: CPU0NSTCKCAL0x3c - System tick calibration for non-secure part of CPU0
cpu1tckcal: CPU1TCKCAL0x40 - System tick calibration for CPU1
nmisrc: NMISRC0x48 - NMI Source Select
presetctrl0: PRESETCTRL00x100 - Peripheral reset control 0
presetctrl1: PRESETCTRL10x104 - Peripheral reset control 1
presetctrl2: PRESETCTRL20x108 - Peripheral reset control 2
presetctrlset: [PRESETCTRLSET; 3]0x120 - Peripheral reset control set register
presetctrlclr: [PRESETCTRLCLR; 3]0x140 - Peripheral reset contro clearl register
swr_reset: SWR_RESET0x160 - generate a software_reset
ahbclkctrl0: AHBCLKCTRL00x200 - AHB Clock control 0
ahbclkctrl1: AHBCLKCTRL10x204 - AHB Clock control 1
ahbclkctrl2: AHBCLKCTRL20x208 - AHB Clock control 2
ahbclkctrlset: [AHBCLKCTRLSET; 3]0x220 - Peripheral reset control register
ahbclkctrlclr: [AHBCLKCTRLCLR; 3]0x240 - Peripheral reset control register
systickclksel0: SYSTICKCLKSEL00x260 - System Tick Timer for CPU0 source select
systickclksel1: SYSTICKCLKSEL10x264 - System Tick Timer for CPU1 source select
traceclksel: TRACECLKSEL0x268 - Trace clock source select
ctimerclksel0: CTIMERCLKSEL00x26c - CTimer 0 clock source select
ctimerclksel1: CTIMERCLKSEL10x270 - CTimer 1 clock source select
ctimerclksel2: CTIMERCLKSEL20x274 - CTimer 2 clock source select
ctimerclksel3: CTIMERCLKSEL30x278 - CTimer 3 clock source select
ctimerclksel4: CTIMERCLKSEL40x27c - CTimer 4 clock source select
mainclksela: MAINCLKSELA0x280 - Main clock A source select
mainclkselb: MAINCLKSELB0x284 - Main clock source select
clkoutsel: CLKOUTSEL0x288 - CLKOUT clock source select
pll0clksel: PLL0CLKSEL0x290 - PLL0 clock source select
pll1clksel: PLL1CLKSEL0x294 - PLL1 clock source select
adcclksel: ADCCLKSEL0x2a4 - ADC clock source select
usb0clksel: USB0CLKSEL0x2a8 - FS USB clock source select
usb1clksel: USB1CLKSEL0x2ac - HS USB clock source select - NOT USED
fcclksel0: FCCLKSEL00x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider
fcclksel1: FCCLKSEL10x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider
fcclksel2: FCCLKSEL20x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider
fcclksel3: FCCLKSEL30x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider
fcclksel4: FCCLKSEL40x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider
fcclksel5: FCCLKSEL50x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider
fcclksel6: FCCLKSEL60x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider
fcclksel7: FCCLKSEL70x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider
hslspiclksel: HSLSPICLKSEL0x2d0 - HS LSPI clock source select
mclkclksel: MCLKCLKSEL0x2e0 - MCLK clock source select
sctclksel: SCTCLKSEL0x2f0 - SCTimer/PWM clock source select
sdioclksel: SDIOCLKSEL0x2f8 - SDIO clock source select
systickclkdiv0: SYSTICKCLKDIV00x300 - System Tick Timer divider for CPU0
systickclkdiv1: SYSTICKCLKDIV10x304 - System Tick Timer divider for CPU1
traceclkdiv: TRACECLKDIV0x308 - TRACE clock divider
flexfrg0ctrl: FLEXFRG0CTRL0x320 - Fractional rate divider for flexcomm 0
flexfrg1ctrl: FLEXFRG1CTRL0x324 - Fractional rate divider for flexcomm 1
flexfrg2ctrl: FLEXFRG2CTRL0x328 - Fractional rate divider for flexcomm 2
flexfrg3ctrl: FLEXFRG3CTRL0x32c - Fractional rate divider for flexcomm 3
flexfrg4ctrl: FLEXFRG4CTRL0x330 - Fractional rate divider for flexcomm 4
flexfrg5ctrl: FLEXFRG5CTRL0x334 - Fractional rate divider for flexcomm 5
flexfrg6ctrl: FLEXFRG6CTRL0x338 - Fractional rate divider for flexcomm 6
flexfrg7ctrl: FLEXFRG7CTRL0x33c - Fractional rate divider for flexcomm 7
ahbclkdiv: AHBCLKDIV0x380 - System clock divider
clkoutdiv: CLKOUTDIV0x384 - CLKOUT clock divider
frohfdiv: FROHFDIV0x388 - FRO_HF (96MHz) clock divider
wdtclkdiv: WDTCLKDIV0x38c - WDT clock divider
adcclkdiv: ADCCLKDIV0x394 - ADC clock divider
usb0clkdiv: USB0CLKDIV0x398 - USB0 Clock divider
mclkdiv: MCLKDIV0x3ac - I2S MCLK clock divider
sctclkdiv: SCTCLKDIV0x3b4 - SCT/PWM clock divider
sdioclkdiv: SDIOCLKDIV0x3bc - SDIO clock divider
pll0clkdiv: PLL0CLKDIV0x3c4 - PLL0 clock divider
clockgenupdatelockout: CLOCKGENUPDATELOCKOUT0x3fc - Control clock configuration registers access (like xxxDIV, xxxSEL)
fmccr: FMCCR0x400 - FMC configuration register - INTERNAL USE ONLY
usb0clkctrl: USB0CLKCTRL0x40c - USB0 clock control
usb0clkstat: USB0CLKSTAT0x410 - USB0 clock status
fmcflush: FMCFLUSH0x41c - FMCflush control
mclkio: MCLKIO0x420 - MCLK control
usb1clkctrl: USB1CLKCTRL0x424 - USB1 clock control
usb1clkstat: USB1CLKSTAT0x428 - USB1 clock status
flashbankenable: FLASHBANKENABLE0x450 - Flash Banks control
sdioclkctrl: SDIOCLKCTRL0x460 - SDIO CCLKIN phase and delay control
pll1ctrl: PLL1CTRL0x560 - PLL1 550m control
pll1stat: PLL1STAT0x564 - PLL1 550m status
pll1ndec: PLL1NDEC0x568 - PLL1 550m N divider
pll1mdec: PLL1MDEC0x56c - PLL1 550m M divider
pll1pdec: PLL1PDEC0x570 - PLL1 550m P divider
pll0ctrl: PLL0CTRL0x580 - PLL0 550m control
pll0stat: PLL0STAT0x584 - PLL0 550m status
pll0ndec: PLL0NDEC0x588 - PLL0 550m N divider
pll0pdec: PLL0PDEC0x58c - PLL0 550m P divider
pll0sscg0: PLL0SSCG00x590 - PLL0 Spread Spectrum Wrapper control register 0
pll0sscg1: PLL0SSCG10x594 - PLL0 Spread Spectrum Wrapper control register 1
efuseclkctrl: EFUSECLKCTRL0x5cc - eFUSE controller clock enable
starter0: STARTER00x680 - Start logic wake-up enable register
starter1: STARTER10x684 - Start logic wake-up enable register
starterset0: STARTERSET00x6a0 - Set bits in STARTER
starterset1: STARTERSET10x6a4 - Set bits in STARTER
starterclr0: STARTERCLR00x6c0 - Clear bits in STARTER
starterclr1: STARTERCLR10x6c4 - Clear bits in STARTER
hardwaresleep: HARDWARESLEEP0x780 - Hardware Sleep control
cpuctrl: CPUCTRL0x800 - CPU Control for multiple processors
cpboot: CPBOOT0x804 - Coprocessor Boot Address
cpstack: CPSTACK0x808 - Coprocessor Stack Address
cpstat: CPSTAT0x80c - CPU Status
dice_reg0: DICE_REG00x900 - Composite Device Identifier
dice_reg1: DICE_REG10x904 - Composite Device Identifier
dice_reg2: DICE_REG20x908 - Composite Device Identifier
dice_reg3: DICE_REG30x90c - Composite Device Identifier
dice_reg4: DICE_REG40x910 - Composite Device Identifier
dice_reg5: DICE_REG50x914 - Composite Device Identifier
dice_reg6: DICE_REG60x918 - Composite Device Identifier
dice_reg7: DICE_REG70x91c - Composite Device Identifier
clock_ctrl: CLOCK_CTRL0xa18 - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures
comp_int_ctrl: COMP_INT_CTRL0xb10 - Comparator Interrupt control
comp_int_status: COMP_INT_STATUS0xb14 - Comparator Interrupt status
autoclkgateoverride: AUTOCLKGATEOVERRIDE0xe04 - Control automatic clock gating
gpiopsync: GPIOPSYNC0xe08 - Enable bypass of the first stage of synchonization inside GPIO_INT module
debug_lock_en: DEBUG_LOCK_EN0xfa0 - Control write access to security registers -- FOR INTERNAl USE ONLY
debug_features: DEBUG_FEATURES0xfa4 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY
debug_features_dp: DEBUG_FEATURES_DP0xfa8 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY
codesecurityprottest: CODESECURITYPROTTEST0xfb0 - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY
codesecurityprotcpu0: CODESECURITYPROTCPU00xfb4 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
codesecurityprotcpu1: CODESECURITYPROTCPU10xfb8 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY
key_block: KEY_BLOCK0xfbc - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY
debug_auth_scratch: DEBUG_AUTH_SCRATCH0xfc0 - Debug authentication scratch registers -- FOR INTERNAL USE ONLY
cpucfg: CPUCFG0xfd4 - CPUs configuration register
periphencfg: PERIPHENCFG0xfec - peripheral enable configuration -- FOR INTERNAL USE ONLY
device_id0: DEVICE_ID00xff8 - Device ID
dieid: DIEID0xffc - Chip revision ID and Number
Auto Trait Implementations
impl Send for RegisterBlock
impl !Sync for RegisterBlock
Blanket Implementations
impl<T> From<T> for T[src]
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
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The type returned in the event of a conversion error.
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impl<T, U> Into<U> for T where
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The type returned in the event of a conversion error.
fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
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T: ?Sized, [src]
T: ?Sized,
fn borrow_mut(&mut self) -> &mut T[src]
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Should always be Self