Struct lpc55s6x_pac::syscon::sdioclkctrl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn cclk_drv_phase(&self) -> CCLK_DRV_PHASER

Bits 0:1 - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.

pub fn cclk_sample_phase(&self) -> CCLK_SAMPLE_PHASER

Bits 2:3 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn phase_active(&self) -> PHASE_ACTIVER

Bit 7 - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.

pub fn cclk_drv_delay(&self) -> CCLK_DRV_DELAYR

Bits 16:20 - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.

pub fn cclk_drv_delay_active(&self) -> CCLK_DRV_DELAY_ACTIVER

Bit 23 - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.

pub fn cclk_sample_delay(&self) -> CCLK_SAMPLE_DELAYR

Bits 24:28 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn cclk_sample_delay_active(&self) -> CCLK_SAMPLE_DELAY_ACTIVER

Bit 31 - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.