Struct lpc55s6x_pac::syscon::pll0ctrl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn selr(&self) -> SELRR

Bits 0:3 - Bandwidth select R value.

pub fn seli(&self) -> SELIR

Bits 4:9 - Bandwidth select I value.

pub fn selp(&self) -> SELPR

Bits 10:14 - Bandwidth select P value.

pub fn bypasspll(&self) -> BYPASSPLLR

Bit 15 - Bypass PLL input clock is sent directly to the PLL output (default).

pub fn bypasspostdiv2(&self) -> BYPASSPOSTDIV2R

Bit 16 - bypass of the divide-by-2 divider in the post-divider.

pub fn limupoff(&self) -> LIMUPOFFR

Bit 17 - limup_off = 1 in spread spectrum and fractional PLL applications.

pub fn bwdirect(&self) -> BWDIRECTR

Bit 18 - Control of the bandwidth of the PLL.

pub fn bypassprediv(&self) -> BYPASSPREDIVR

Bit 19 - bypass of the pre-divider.

pub fn bypasspostdiv(&self) -> BYPASSPOSTDIVR

Bit 20 - bypass of the post-divider.

pub fn clken(&self) -> CLKENR

Bit 21 - enable the output clock.

pub fn frmen(&self) -> FRMENR

Bit 22 - free running mode.

pub fn frmclkstable(&self) -> FRMCLKSTABLER

Bit 23 - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable.

pub fn skewen(&self) -> SKEWENR

Bit 24 - skew mode.