Struct lpc55s6x_pac::spi0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cfg: CFG,
    pub dly: DLY,
    pub stat: STAT,
    pub intenset: INTENSET,
    pub intenclr: INTENCLR,
    pub div: DIV,
    pub intstat: INTSTAT,
    pub fifocfg: FIFOCFG,
    pub fifostat: FIFOSTAT,
    pub fifotrig: FIFOTRIG,
    pub fifointenset: FIFOINTENSET,
    pub fifointenclr: FIFOINTENCLR,
    pub fifointstat: FIFOINTSTAT,
    pub fifowr: FIFOWR,
    pub fiford: FIFORD,
    pub fifordnopop: FIFORDNOPOP,
    pub id: ID,
    // some fields omitted
}

Register block

Fields

cfg: CFG

0x400 - SPI Configuration register

dly: DLY

0x404 - SPI Delay register

stat: STAT

0x408 - SPI Status. Some status flags can be cleared by writing a 1 to that bit position.

intenset: INTENSET

0x40c - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

intenclr: INTENCLR

0x410 - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

div: DIV

0x424 - SPI clock Divider

intstat: INTSTAT

0x428 - SPI Interrupt Status

fifocfg: FIFOCFG

0xe00 - FIFO configuration and enable register.

fifostat: FIFOSTAT

0xe04 - FIFO status register.

fifotrig: FIFOTRIG

0xe08 - FIFO trigger settings for interrupt and DMA request.

fifointenset: FIFOINTENSET

0xe10 - FIFO interrupt enable set (enable) and read register.

fifointenclr: FIFOINTENCLR

0xe14 - FIFO interrupt enable clear (disable) and read register.

fifointstat: FIFOINTSTAT

0xe18 - FIFO interrupt status register.

fifowr: FIFOWR

0xe20 - FIFO write data.

fiford: FIFORD

0xe30 - FIFO read data.

fifordnopop: FIFORDNOPOP

0xe40 - FIFO data read with no FIFO pop.

id: ID

0xffc - Peripheral identification register.