Enum lpc55s6x_pac::rtc::ctrl::RTC_SUBSEC_ENAW

pub enum RTC_SUBSEC_ENAW {
    POWER_UP,
    POWERED_DOWN,
}

Values that can be written to the field RTC_SUBSEC_ENA

Variants

POWER_UP

The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'.

POWERED_DOWN

The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode.