[−][src]Enum lpc55s6x_pac::i2s0::fifointenset::RXLVLR
Possible values of the field RXLVL
Variants
DISABLED
No interrupt will be generated based on the RX FIFO level.
ENABLED
If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.
Methods
impl RXLVLR
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pub fn bit_is_clear(&self) -> bool
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Returns true
if the bit is clear (0)
pub fn bit_is_set(&self) -> bool
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Returns true
if the bit is set (1)
pub fn bit(&self) -> bool
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Value of the field as raw bits
pub fn is_disabled(&self) -> bool
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Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool
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Checks if the value of the field is ENABLED
Trait Implementations
impl PartialEq<RXLVLR> for RXLVLR
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impl Copy for RXLVLR
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impl Debug for RXLVLR
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impl Clone for RXLVLR
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Auto Trait Implementations
Blanket Implementations
impl<T> From<T> for T
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impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Same<T> for T
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type Output = T
Should always be Self