Struct lpc55s6x_pac::ctimer0::mcr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn mr0i(&self) -> MR0IR

Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.

pub fn mr0r(&self) -> MR0RR

Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it.

pub fn mr0s(&self) -> MR0SR

Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.

pub fn mr1i(&self) -> MR1IR

Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.

pub fn mr1r(&self) -> MR1RR

Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it.

pub fn mr1s(&self) -> MR1SR

Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.

pub fn mr2i(&self) -> MR2IR

Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.

pub fn mr2r(&self) -> MR2RR

Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it.

pub fn mr2s(&self) -> MR2SR

Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.

pub fn mr3i(&self) -> MR3IR

Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.

pub fn mr3r(&self) -> MR3RR

Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it.

pub fn mr3s(&self) -> MR3SR

Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.

pub fn mr0rl(&self) -> MR0RLR

Bit 24 - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

pub fn mr1rl(&self) -> MR1RLR

Bit 25 - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

pub fn mr2rl(&self) -> MR2RLR

Bit 26 - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).

pub fn mr3rl(&self) -> MR3RLR

Bit 27 - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR).