Struct lpc55s6x_pac::anactrl::ringo1_ctrl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn s(&self) -> SR

Bit 0 - Select short or long ringo (for all ringos types).

pub fn fs(&self) -> FSR

Bit 1 - Ringo frequency output divider.

pub fn pd(&self) -> PDR

Bit 2 - Ringo module Power control.

pub fn e_r24(&self) -> E_R24R

Bit 3 - .

pub fn e_r35(&self) -> E_R35R

Bit 4 - .

pub fn e_m2(&self) -> E_M2R

Bit 5 - Metal 2 (M2) monitor control.

pub fn e_m3(&self) -> E_M3R

Bit 6 - Metal 3 (M3) monitor control.

pub fn e_m4(&self) -> E_M4R

Bit 7 - Metal 4 (M4) monitor control.

pub fn e_m5(&self) -> E_M5R

Bit 8 - Metal 5 (M5) monitor control.

pub fn divisor(&self) -> DIVISORR

Bits 16:19 - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)

pub fn div_update_req(&self) -> DIV_UPDATE_REQR

Bit 31 - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete.