Struct lpc55s6x_pac::usbphy::pll_sic::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn misc2_control0(&self) -> MISC2_CONTROL0R

Bit 5 - Modifies the operation of the pll_sic_power_int signal

pub fn pll_en_usb_clks(&self) -> PLL_EN_USB_CLKSR

Bit 6 - Enables the USB clock from PLL to USB PHY

pub fn pll_power(&self) -> PLL_POWERR

Bit 12 - Power up the USB PLL

pub fn pll_enable(&self) -> PLL_ENABLER

Bit 13 - Enables the clock output from the USB PLL

pub fn pll_bypass(&self) -> PLL_BYPASSR

Bit 16 - Bypass the USB PLL.

pub fn refbias_pwd_sel(&self) -> REFBIAS_PWD_SELR

Bit 19 - Reference bias power down select.

pub fn refbias_pwd(&self) -> REFBIAS_PWDR

Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.

pub fn pll_reg_enable(&self) -> PLL_REG_ENABLER

Bit 21 - This field controls the USB PLL regulator, set to enable the regulator

pub fn pll_div_sel(&self) -> PLL_DIV_SELR

Bits 22:24 - This field controls the USB PLL feedback loop divider

pub fn pll_lock(&self) -> PLL_LOCKR

Bit 31 - USB PLL lock status indicator