Struct lpc55s6x_pac::syscon::sdioclkctrl::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn cclk_drv_phase(&mut self) -> _CCLK_DRV_PHASEW

Bits 0:1 - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.

pub fn cclk_sample_phase(&mut self) -> _CCLK_SAMPLE_PHASEW

Bits 2:3 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn phase_active(&mut self) -> _PHASE_ACTIVEW

Bit 7 - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.

pub fn cclk_drv_delay(&mut self) -> _CCLK_DRV_DELAYW

Bits 16:20 - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.

pub fn cclk_drv_delay_active(&mut self) -> _CCLK_DRV_DELAY_ACTIVEW

Bit 23 - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.

pub fn cclk_sample_delay(&mut self) -> _CCLK_SAMPLE_DELAYW

Bits 24:28 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn cclk_sample_delay_active(&mut self) -> _CCLK_SAMPLE_DELAY_ACTIVEW

Bit 31 - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.