Struct lpc55s6x_pac::sdif::status::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn fifo_rx_watermark(&self) -> FIFO_RX_WATERMARKR

Bit 0 - FIFO reached Receive watermark level; not qualified with data transfer.

pub fn fifo_tx_watermark(&self) -> FIFO_TX_WATERMARKR

Bit 1 - FIFO reached Transmit watermark level; not qualified with data transfer.

pub fn fifo_empty(&self) -> FIFO_EMPTYR

Bit 2 - FIFO is empty status.

pub fn fifo_full(&self) -> FIFO_FULLR

Bit 3 - FIFO is full status.

pub fn cmdfsmstates(&self) -> CMDFSMSTATESR

Bits 4:7 - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The command FSM state is represented using 19 bits.

pub fn data_3_status(&self) -> DATA_3_STATUSR

Bit 8 - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present.

pub fn data_busy(&self) -> DATA_BUSYR

Bit 9 - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy.

pub fn data_state_mc_busy(&self) -> DATA_STATE_MC_BUSYR

Bit 10 - Data transmit or receive state-machine is busy.

pub fn response_index(&self) -> RESPONSE_INDEXR

Bits 11:16 - Index of previous response, including any auto-stop sent by core.

pub fn fifo_count(&self) -> FIFO_COUNTR

Bits 17:29 - FIFO count - Number of filled locations in FIFO.

pub fn dma_ack(&self) -> DMA_ACKR

Bit 30 - DMA acknowledge signal state.

pub fn dma_req(&self) -> DMA_REQR

Bit 31 - DMA request signal state.