Struct lpc55s6x_pac::dgbmailbox::csw::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn resynch_req(&mut self) -> _RESYNCH_REQW

Bit 0 - Debugger will set this bit to 1 to request a resynchronrisation

pub fn req_pending(&mut self) -> _REQ_PENDINGW

Bit 1 - Request is pending from debugger (i.e unread value in REQUEST)

pub fn dbg_or_err(&mut self) -> _DBG_OR_ERRW

Bit 2 - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)

pub fn ahb_or_err(&mut self) -> _AHB_OR_ERRW

Bit 3 - AHB overrun Error (Return value overwritten by ROM)

pub fn soft_reset(&mut self) -> _SOFT_RESETW

Bit 4 - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to this bit will cause a soft reset for DM.

pub fn chip_reset_req(&mut self) -> _CHIP_RESET_REQW

Bit 5 - Write only bit. Once written will cause the chip to reset (note that the DM is not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event)