Struct lpc55s6x_pac::anactrl::ringo0_ctrl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn sl(&self) -> SLR

Bit 0 - Select short or long ringo (for all ringos types).

pub fn fs(&self) -> FSR

Bit 1 - Ringo frequency output divider.

pub fn swn_swp(&self) -> SWN_SWPR

Bits 2:3 - PN-Ringos (P-Transistor and N-Transistor processing) control.

pub fn pd(&self) -> PDR

Bit 4 - Ringo module Power control.

pub fn e_nd0(&self) -> E_ND0R

Bit 5 - First NAND2-based ringo control.

pub fn e_nd1(&self) -> E_ND1R

Bit 6 - Second NAND2-based ringo control.

pub fn e_nr0(&self) -> E_NR0R

Bit 7 - First NOR2-based ringo control.

pub fn e_nr1(&self) -> E_NR1R

Bit 8 - Second NOR2-based ringo control.

pub fn e_iv0(&self) -> E_IV0R

Bit 9 - First Inverter-based ringo control.

pub fn e_iv1(&self) -> E_IV1R

Bit 10 - Second Inverter-based ringo control.

pub fn e_pn0(&self) -> E_PN0R

Bit 11 - First PN (P-Transistor and N-Transistor processing) monitor control.

pub fn e_pn1(&self) -> E_PN1R

Bit 12 - Second PN (P-Transistor and N-Transistor processing) monitor control.

pub fn divisor(&self) -> DIVISORR

Bits 16:19 - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16)

pub fn div_update_req(&self) -> DIV_UPDATE_REQR

Bit 31 - Ringo clock out Divider status flag. Set when a change is made to the divider value, cleared when the change is complete.